Phase-Locked Loop Comparison - 28nm Tapeout

Comparing All-Digital (AD) vs Analog Mixed-Signal (AMS) Phase-Locked Loops (PLL)

Course: 18‑525/18‑725 Advanced Digital Integrated Circuit Design (CMU)

Team: PLL Pals — Hsien‑Fu Hung, Jason Lee, Tristan Liu, Roman Kapur, Gongwei Wang

Process / Die: TSMC 28 nm, within a 1 mm² die

Goal: Tape out both an All‑Digital PLL (ADPLL) and an Analog/Mixed‑Signal PLL (AMS PLL) on the same node to directly compare area, power, jitter, lock time, and design complexity.

Overview

Our chip integrates both an ADPLL and an AMS PLL, locking a 20 MHz reference to a ~1.2–2.4 GHz output range. The ADPLL uses binary-search frequency acquisition, a bang‑bang phase detector (BBPD), and a fully synthesizable DCO; the AMS PLL implements a source‑switched charge pump, second‑order loop filter, and a 7‑stage ring‑oscillator VCO. Bring‑up is planned for Fall 2025.

Final Design Specs

Key specs from post‑layout sims (@ ~2 GHz):

Specs measured at layout stage; AMS jitter also summarized as ~2.5 ps with 2 GHz clock (≈1.5% at 3σ).

ADPLL settings: 5‑bit DCO tuning (32 steps), ≈876 MHz–3.26 GHz range with 20–30 ps step size; scannable initial step for acquisition.

AMS PLL settings: CP currents 4 µA / 2 µA / 1 µA (combinable), loop‑filter caps 1×C1 / 0.5×C1 / 0.25×C1 (to 1.75×C1 max), resistors 1×R2 / 0.5×R2 / 0.25×R2; output divider ÷16/32/64.

AMS testing I/O: 2‑bit address + 3‑bit enables (5 pins) select CP current, LF C/R settings, and output‑driver path.

Design Choices

Why AMS choices:

• Source‑switched charge pump → higher output resistance & lower feedthrough vs drain‑switched; constant‑gm bias with selectable 4/2/1 µA settings.
• Second‑order loop filter chosen for stability/lock‑time trade‑off; target ~1–2 MHz BW (~1/10–1/20 of 20 MHz ref); example values C1 = 500 fF, R2 = 33 kΩ, C2 = 8.78 pF.
• 7‑stage ring‑oscillator VCO → lower design complexity vs LC, adequate jitter across target range; guarded layout with DNW and symmetry care.

Why AD choices:

• Fully synthesizable DCO (library‑cell buffers) for portability and ease of integration.
• Bang‑bang PD + counter‑based acquisition to handle 20 MHz ref and large divide ratios robustly.

System‑level rationale: Co‑fabricating both architectures on the same 28 nm die enables apples‑to‑apples comparison of area/power/jitter/lock time for future system design choices.

Story of Creation

This project was an adventure. 18‑525/18‑725 lets CMU students tape out almost anything within ~1 mm² on TSMC N28. Some teams collaborate with labs (and occasionally secure extra funding); others build passion projects (e.g., a prior team recreated the original Game Boy). Despite the “Digital” title, AMS or even fully analog designs are fair game.

From day one, we aimed to exercise AMS skills with a PLL comparison. A friend’s father at MediaTek suggested PLLs because they’re well documented and split cleanly across AD and AMS work. I focused primarily on the AMS PLL and later top‑level integration; two teammates handled the ADPLL, and three of us worked the AMS PLL.

Our first major hurdle: PDK access lag. We didn’t get the TSMC N28 PDK until ~week 7 (around spring break), effectively compressing a 14‑week semester into < 2 months of real design time. That shaped our scope: an integer‑N baseline with hooks toward a DSM fractional‑N path post‑silicon.

Top‑level bring‑up required significant flow hacking. The class scripts are tuned for digital; analog support is thinner. We iterated PnR + analog integration repeatedly, validated with DRC/LVS, and simulated heavily. Runtime was painful: full‑loop sims took hours; top‑level chip transient ran ~24 hours and consumed ~1 TB scratch for a simple 4 µs window.

We taped out successfully and will evaluate silicon in Fall 2025. Future work: add the delta‑sigma modulator for fractional‑N and extend on‑chip testability.