Experience Projects

Hi, my name is

Roman Kapur

I'm a masters student studying electrical & computer engineering at Carnegie Mellon University interested in digital design and computer architecture.

Experience

Advanced Micro Devices logo
Advanced Micro Devices

HWE Intern - SoC Design

May 2025 – Aug 2025
Python Verilog
Advanced Micro Devices logo
Advanced Micro Devices

HWE Intern - Yield Engineering

Jun 2024 – Aug 2024
Python Snowflake TCL
Sandia National Labs logo
Sandia National Labs

SWE Intern - Systems R&D

May 2023 – Aug 2023
MATLAB
Thornton Tomasetti logo
Thornton Tomasetti

SWE Intern - Automation

May 2022 – Aug 2022
Python Visual Basic

Projects

Comparison of PLL Architectures

Designed and fabricated a 1 mm² TSMC 28 nm chip integrating both an all‑digital and an analog/mixed‑signal phase locked loop

Full PosterVideo Presentation
Verilog Virtuoso Genus Innovus TCL

Intel Semiconductor Yield Prediction with Machine Learning

Analyzed half‑million‑row wafer datasets to predict defective chips using feature engineering, CatBoost modeling, and cost‑optimized thresholding, improving defect detection and reducing manufacturing losses.

Full Slide Deck
Python Scikit-Learn

Pixel Image Sensor

Pixel image sensor interface

Full Slide Deck
Virtuoso Innovus TCL

Digital Logic & Hardware Systems

Built high‑performance hardware systems, including a fast matrix calculator, a network‑on‑chip, and a USB 2.0 protocol engine

Slide Deck
Verilog Quartus